This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-127353, filed Apr. 26, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor device comprising at least a memory and a logic circuit merged on a single chip and a method of manufacturing the same.
2. Description of the Related Art
Semiconductor devices including high performance logic devices such as CPUs and high speed SRAMs need to suppress delays of signal propagation so as to be able to operate at high speed. Therefore, it is desirable to use multilayer wiring for such devices in order to reduce the wiring resistance thereof. It is also desirable to use copper (Cu) as wiring material because of the low electric resistance of the metal. Furthermore, a material having a specific dielectric constant (k) lower than SiO2 film needs to be used as insulating film for the purpose of electrically insulating wiring layers from each other.
So called low-k film, for example, MSX (methyl-polysiloxane), HSQ (hydrogen-silsesquioxane) or PAE (poly(arylene)ether) is known as insulating film having a low dielectric constant. Low-k films of this type normally show a specific dielectric constant of k=2.6 to 3.0 and hence is lower than the specific dielectric constant of SiO2 film, of k=3.5 to 4.3. Therefore, low-k film can take a major role in reducing the delay time. So-called porous low-k film has also been developed as the film density of low-k film can be reduced by using a porous material for the low-k film.
Meanwhile, semiconductor devices comprising a high performance logic circuit and a memory such as a DRAM merged on a single chip also require a multilayer wiring arrangement of using Cu wires and a low-k material for the purpose of improving the performance.
However, as a multilayer wiring arrangement is used, the reliability problem of the underlying transistors becomes apparent. Generally, when a CMOS device is held to temperature of about 150xc2x0 C. while a weak electric field is applied to the gate electrode of the P-channel MOS transistor (PMOS) of the CMOS device, a new level and a fixed positive electric charge are produced along the interface of the gate insulating films and the silicon. Then, it is known that there arises a phenomenon including a change in the threshold voltage of the transistor, which is referred to as NBTI (Negative Bias Temperature Instability) degradation, to deteriorate the long term reliability of the characteristics of the device. C. E. Blat et al., J. Appl. Phys. Vol. 69, p. 1712 (1991) describes a possible cause of the phenomenon. According to the above identified paper, H2O (gas) that is diffused to get to the flaws formed on the interface of the gate insulating films and the silicon shows a hole catching reaction due to the electric field and the heat there, and consequently produces a new level and a fixed positive electric charge. Therefore, in order to suppress the possible NBTI degradation in the process of forming a device that is sensitive to NBTI degradation, it is necessary to prevent H2O from diffusing to the element forming layers including the gate insulating films.
Additionally, a so-called H2 sintering treatment of thermally treating a semiconductor device in an H2 gas atmosphere is conducted immediately before the end of the process of manufacturing the device. The H2 sintering treatment is designed to recover the semiconductor device from the charging damages that have been caused by the plasma treatments such as reactive ion etching and plasma CVD conducted in the device manufacturing process. However, the phenomenon of NBTI degradation can occur when H2 gas is excessively introduced into the substrate in the H2 sintering treatment as in the case of the use of H2O.
There is also known a problem that NBTI degradation is accelerated when low-k film is used for multilayer wiring if such undesired gases are diffused into the element forming layers at a high rate. This is because firstly a low-k material discharges H2O and H2 at a rate higher than SiO2 film during the film forming process and secondly a low-k material shows a high hygroscopicity and hence discharges H2O generously in the heat treatment process that comes after the low-k film forming process. Therefore, when a low-k material is used for manufacturing a high performance device, it is subjected to a number of restrictions including a material that shows a low H2O and H2 emission rate has to be selected for the film forming process, and a low upper temperature limit has to be selected for the heat treatment in the multilayer wiring process.
Furthermore, in a semiconductor device comprising a logic circuit and a DRAM merged on a single chip, the reliability of the transistors in the logic region of the device can be deteriorated due to NBTI degradation particularly when H2 is introduced excessively into the substrate. On the other hand, the DRAM region has to be subjected to H2 sintering for a long period of time at high temperature in order to prolong the retention time because the latter significantly influence the data retaining characteristics of the device. In short, the logic region and the DRAM region of the device have respective requirements that are contradictory relative to each other. This means that it is difficult to establish both a high degree of reliability of the transistors in the logic region and excellent data retaining characteristics of the DRAM region. Thus, there is a demand for semiconductor devices that can provide both a high degree of reliability of the transistors in the logic region and excellent data retaining characteristics of the DRAM region and also for a method of manufacturing such devices.
According to an aspect of the invention, there is provided a semiconductor device comprising: a semiconductor substrate; a logic region formed in the semiconductor substrate and including an element forming layer; a memory region formed in the semiconductor substrate and including an element forming layer; a multilayer wiring layer formed above each of the logic region and the memory region; and a diffusion preventing film formed at least between the multilayer wiring layer in the logic region and the element forming layer in the logic region; the diffusion preventing film being adapted to prevent H2O from diffusing into the logic region.
According to another aspect of the invention, there is provided a method of manufacturing a semiconductor device comprising: forming transistors in a logic region and a memory region of a semiconductor substrate; forming a first insulating film on the logic region and the memory region; forming a diffusion preventing film on the first insulating film in the logic region; the diffusion preventing film preventing H2O from diffusion; forming a second insulating film on the diffusion preventing film and the memory region; and forming a multilayer wiring layer on the second insulating film.